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Noise characterization of IUCAA digital sampling array controller

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dc.contributor.author Rikame, Ketan en_US
dc.contributor.author Chattopadhyay, Sabyasachi et al. en_US
dc.date.accessioned 2019-09-09T11:26:40Z
dc.date.available 2019-09-09T11:26:40Z
dc.date.issued 2018-07 en_US
dc.identifier.citation Journal of Astronomical Telescopes, Instruments, and Systems, 4(3), 036002. en_US
dc.identifier.issn 2329-4124 en_US
dc.identifier.issn 2329-4221 en_US
dc.identifier.uri http://dr.iiserpune.ac.in:8080/xmlui/handle/123456789/3873
dc.identifier.uri https://doi.org/10.1117/1.JATIS.4.3.036002 en_US
dc.description.abstract The IUCAA digital sampling array controller (IDSAC) is a flexible and generic yet powerful CCD controller that can handle a wide range of scientific detectors. Based on an easily scalable modular backplane architecture consisting of single board controllers (SBC), IDSAC can control large detector arrays and mosaics. Each of the SBCs offers the full functionality required to control a CCD independently. The SBCs can be cold swapped without the need to reconfigure them. IDSAC is also available in a backplane-less architecture. Each SBC can handle data from up to four video channels with or without dummy outputs at speeds up to 500-kilo pixels per second (kPPS) per channel with a resolution of 16 bits. Communication with a Linux-based host computer is through a USB3.0 interface, with the option of using copper or optical fibers. A field programmable gate array (FPGA) is used as the master controller in each SBC, which allows great flexibility in optimizing performance by adjusting gain, timing signals, bias levels, etc., using user-editable configuration files without altering the circuit topology. Elimination of thermal kTC noise is achieved via digital correlated double sampling (DCDS). The number of digital samples per pixel (for both reset and signal levels) is user configurable. We present the results of noise performance characterization of IDSAC through simulation, theoretical modeling, and actual measurements. The contribution of different types of noise sources is modeled using a tool to predict noise of a generic DCDS signal chain analytically. The analytical model predicts the net input referenced noise of the signal chain to be 5 electrons for 200-k pixels/s per channel readout rate with three samples per pixel. Using a cryogenic test setup in the lab, the noise is measured to be 5.4 e (24.3 μV), for the same readout configuration. With a better-optimized configuration of 500-kPPS readout rate, the measured noise is down to 3.8 electrons RMS (17 μV), with three samples per interval. en_US
dc.language.iso en en_US
dc.publisher Society of Photo-Optical Instrumentation Engineers en_US
dc.subject IUCAA digital sampling array controller en_US
dc.subject Flexible and generic yet powerful en_US
dc.subject CCD controller en_US
dc.subject DCDS signal chain analytically en_US
dc.subject DCDS technique for processing en_US
dc.subject 2018 en_US
dc.title Noise characterization of IUCAA digital sampling array controller en_US
dc.type Article en_US
dc.contributor.department Dept. of Physics en_US
dc.identifier.sourcetitle Journal of Astronomical Telescopes, Instruments, and Systems en_US
dc.publication.originofpublisher Foreign en_US


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